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HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
Integrated Device Technology, Inc.
IDT70V07S/L
FEATURES:
* True Dual-Ported memory cells which allow simultaneous access of the same memory location * High-speed access -- Commercial: 25/35/55ns (max.) * Low-power operation -- IDT70V07S Active: 450mW (typ.) Standby: 5mW (typ.) -- IDT70V07L Active: 450mW (typ.) Standby: 5mW (typ.) * IDT70V07 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device * M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave * Busy and Interrupt Flags
* On-chip port arbitration logic * Full on-chip hardware support of semaphore signaling between ports * Fully asynchronous operation from either port * Devices are capable of withstanding greater than 2001V electrostatic discharge * LVTTL-compatible, single 3.3V (0.3V) power supply * Available in 68-pin PGA, 68-pin PLCC, and a 64-pin TQFP
DESCRIPTION:
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT70V07 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.
FUNCTIONAL BLOCK DIAGRAM
OEL OER
R/WR
CEL
R/WL
CER
I/O0L- I/O7L I/O Control I/O Control
I/O0R-I/O7R
BUSYL
(1,2)
BUSYR
Address Decoder
15
(1,2)
A14L A0L
MEMORY ARRAY
Address Decoder
A14R A0R
15
OEL
R/WL
CEL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CER
OER
R/WR
SEML
INTL
(2)
M/S
SEMR
INTR
(2)
2943 drw 01
NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2943/3
6.37
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 450mW of power. The IDT70V07 is packaged in a ceramic 68-pin PGA, a 68pin PLCC, and a 80-pin thin plastic quad flatpack (TQFP).
PIN CONFIGURATIONS (1,2)
R/WL I/O1L I/O0L N/C
SEML
4
INDEX I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
9
8
7
6
5
3
A14L A13L VCC A12L A11L A10L A9L A8L A7L A6L
2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
OEL
CEL
IDT70V07 J68-1 PLCC TOP VIEW(3)
A5L A4L A3L A2L A1L A0L
INTL
BUSYL
GND M/S
INTR
BUSYR
A0R A1R A2R A3R A4R
2943 drw 02
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OER
SEMR
R/WR
CER
I/O7R N/C
A14R A13R GND A12R A11R A10R A9R A8R A7R A6R A5R
I/O1L I/O0L N/C
R/WL
SEML
INDEX N/C I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC N/C GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
N/C A14L A13L VCC A12L A11L A10L A9L A8L A7L A6L N/C N/C
OEL
CEL
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
70V07 PN80-1 TQFP TOP VIEW(3)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
N/C A5L A4L A3L A2L A1L A0L
INTL
BUSYL
GND M/S
INTR
BUSYR
A0R A1R A2R A3R A4R N/C N/C
2943 drw 03
R/WR
I/O7R N/C
OER
NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate the actual part marking.
6.37
SEMR
N/C A14R A13R GND A12R A11R A10R A9R A8R A7R A6R A5R N/C N/C
CER
2
IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D) (1,2)
51 11 53 A7L 55 A9L A5L 52 A6L 54 A8L 50 A4L 49 A3L 48 A2L 47 A1L 46 44 42 A0L BUSYL M/S 45
INTL
40
INTR
38 A1R
36 A3R 35 A4R 32 A7R 30 A9R 34 A5R 33 A6R 31 A8R
10
43 41 39 37 GND BUSYR A0R A2R
09
08
56 57 A11L A10L 58 59 VCC A12L 61 60 A13L 62
07
IDT70V07 G68-1 68-PIN PGA TOP VIEW (3)
29 28 A11R A10R 26 GND 27 A12R
06
A14L 63
05
SEML
65
CEL
25 24 A14R A13R
64 R/WL
04
OEL
SEMR
20
22
23
CER
03
67 66 I/O0L N/C 1 3 68 I/O1L I/O2L I/O4L 2 4 I/O3L I/O5L B C 5 7 9 11 13 15 GND I/O7L GND I/O1R VCC I/O4R 6 I/O6L D 8 10 12 14 16 VCC I/O0R I/O2R I/O3R I/O5R E F G H J
OER
21 R/WR
02
18 19 I/O7R N/C 17 I/O6R
K
01 A INDEX
L
2943 drw 04
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground
2943 tbl 01
CEL
R/WL
CER
R/WR
OEL
A0L - A14L I/O0L - I/O7L
OER
A0R - A14R I/O0R - I/O7R
SEML INTL BUSYL
M/S VCC
SEMR INTR BUSYR
GND
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE I - NON-CONTENTION READ/WRITE CONTROL
Inputs(1) Outputs
CE
H L L X NOTE:
R/W W X L H X
OE
X X L H
SEM
H H H X
I/O0-7 High-Z DATAIN DATAOUT High-Z Deselected: Power-Down Write to Memory Read Memory Outputs Disabled
Mode
2943 tbl 02
1. A0L -- A14L A0R -- A14R.
TRUTH TABLE II - SEMAPHORE READ/WRITE CONTROL(1)
Inputs Outputs
CE
H H L
R/W W H X
OE
L X X
SEM
L L L
I/O0-7 DATAOUT DATAIN -- Read Data in Semaphore Flag Write I/O0 into Semaphore Flag Not Allowed
Mode
NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
2943 tbl 03
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial Unit -0.5 to +4.6 V
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Ambient Temperature 0C to +70C GND 0V VCC 3.3V 0.3V
2943 tbl 05
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
C C C mA
RECOMMENDED DC OPERATING CONDITIONS (2)
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3(1) Typ. 3.3 0 -- -- Max. Unit 3.6 0 0.8 V V V
2943 tbl 06
VCC+0.3 V
NOTES: 2943 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.3V.
CAPACITANCE(1)
(TA = +25C, f = 1.0MHz)TQFP ONLY
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
NOTES: 2943 tbl 07 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V 0.3V)
IDT70V07S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 3.6V, VIN = 0V to VCC Min. -- -- -- 2.4 Max. 10 10 0.4 -- IDT70V07L Min. -- -- -- 2.4 Max. 5 5 0.4 -- Unit A A V V
2943 tbl 08
CE = VIH, VOUT = 0V to VCC
IOL = 4mA IOH = -4mA
NOTE: 1. At Vcc 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V 0.3V)
70V07X25 Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports -- TTL Level Inputs) Standby Current (One Port -- TTL Level Inputs) ISB3 Full Standby Current (Both Ports -- All CMOS Level Inputs) Test Condition Version COM'L. S L S L S L Typ.(2) 100 100 14 12 50 50 70V07X35 70V07X55 Max. Unit 140 mA 120 30 24 87 75 mA Max. Typ.(2) 170 140 30 24 95 85 90 90 12 10 45 45 Max. Typ.(2) 140 120 30 24 87 75 90 90 12 10 45 45
f = fMAX(3)
CE = VIL, Outputs Open SEM = VIH CER = CEL = VIH SEMR = SEML = VIH CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Open,
ISB1
COM'L.
f = fMAX(3)
ISB2
COM'L.
mA
f = fMAX(3) Both Ports CEL and CER > VCC - 0.2V
SEMR = SEML = VIH
COM'L. S L 1.0 0.2 6 3 1.0 0.2 6 3 1.0 0.2 6 3 mA
ISB4
Full Standby Current (One Port -- All CMOS Level Inputs)
CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open f = fMAX(3)
VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L. S L 60 60 90 80 55 55 85 74 55 55 85 74 mA
NOTES: 2943 tbl 09 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 3.3V, TA = +25C, and are not production tested. ICCDC = 80mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
3.3V
COMMERCIAL TEMPERATURE RANGE
3.3V 590 DATAOUT
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns Max. 1.5V 1.5V Figures 1 and 2
2943 tbl 10
590 DATAOUT
BUSY INT
435
30pF
435
5pF
2943 drw 05
2943 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V07X25 Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time(3) Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1, 2)
IDT70V07X35 Min. 35 -- -- -- 3 3 -- 0 -- 15 -- Max. -- 35 35 20 -- -- 20 -- 35 -- 45
IDT70V07X55 Min. 55 -- -- -- 3 3 -- 0 -- 15 -- Max. -- 55 55 30 -- -- 25 -- 50 -- 65 Unit ns ns ns ns ns ns ns ns ns ns ns
2943 tbl 11
Parameter
Min. 25 -- -- -- 3 3 -- 0
(2)
Max. -- 25 25 15 -- -- 15 -- 25 -- 35
Output High-Z Time(1, 2) Chip Enable to Power Up Time(2) Chip Disable to Power Down Time Semaphore Address Access Time Semaphore Flag Update Pulse (OE or SEM)
-- 15 --
NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. "X" in part numbers indicates power rating (S or L).
TIMING OF POWER-UP POWER-DOWN
CE
ICC ISB
tPU
50%
tPD
50%
2943 drw 07
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF READ CYCLES(5)
tRC ADDR tAA (4) tACE (4) tAOE
(4)
CE
OE
R/W
tLZ DATAOUT
(1)
tOH VALID DATA
(4)
tHZ
(2)
BUSYOUT
tBDD
(3, 4)
2943 drw 08
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT70V07X25 Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time(4) Write Enable to Output in High-Z Output Active from End-of-Write
(1, 2) (1, 2, 4) (1, 2) (3) (3)
IDT70V07X35 Min. 35 30 30 0 25 0 20 -- 0 -- 0 5 5 Max. -- -- -- -- -- -- -- 20 -- 20 -- -- --
IDT70V07X55 Min. 55 45 45 0 40 0 30 -- 0 -- 0 5 5 Max. -- -- -- -- -- -- -- 25 -- 25 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
Min. 25 20 20 0 20 0 15 -- 0 -- 0 5 5
Max. -- -- -- -- -- -- -- 15 -- 15 -- -- --
Address Valid to End-of-Write
SEM Flag Write to Read Time SEM Flag Contention Window
2943 tbl 12 NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. "X" in part numbers indicates power rating (S or L).
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8) W
tWC ADDRESS tHZ
(7)
OE
tAW
CE
or SEM
(9)
tAS(6) R/W tWZ (7) DATAOUT
(4)
tWP(2)
tWR
(3)
tOW
(4)
tDW DATAIN
tDH
2943 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
tWC ADDRESS tAW
CE
or SEM
(9)
tAS(6) R/W
tEW (2)
tWR(3)
tDW DATAIN
tDH
2943 drw 10
NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.37
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tSAA A0-A2 VALID ADDRESS tWR tAW tEW tDW DATAIN VALID tAS R/W tSWRD tAOE tWP tDH VALID ADDRESS tACE tSOP DATAOUT VALID(2)
tOH
SEM
I/O0
OE
Write Cycle Read Cycle
2943 drw 11
NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS A0"B"-A2"B" MATCH
SIDE
(2)
"B"
R/W"B"
SEM"B"
2943 drw 12
NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.37
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT70V07X25 Symbol BUSY TIMING (M/S = VIH) S tBAA tBDA tBAC tBDC tAPS tBDD Parameter Min. -- -- -- -- 5 -- 20 Max. 25 25 25 25 -- 35 -- IDT70V07X35 Min. -- -- -- -- 5 -- 25 Max. 35 35 35 35 -- 40 -- IDT70V07X55 Min. -- -- -- -- 5 -- 25 Max. 45 45 45 45 -- 50 -- Unit ns ns ns ns ns ns ns
BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable Low BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3) Write Hold After BUSY(5) tWH BUSY TIMING (M/S = VIL) S BUSY Input to Write(4) tWB tWH Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay
(1)
0 20 -- --
-- -- 55 50
0 25 -- --
-- -- 65 60
0 25 -- --
-- -- 85 80
ns ns ns ns
2943 tbl 13
NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. "X" in part numbers indicates power rating (S or L).
BUSY".
6.37
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,4,5)
tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS(1) ADDR"B" MATCH tBDA tBDD VALID tDH
BUSY"B"
tWDD DATAOUT "B" tDDD
(3)
2943 drw 13
VALID
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH (1)
R/W"B"
(2) 2943 drw 14
NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
6.37
11
IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1)
ADDR"A" and "B"
ADDRESSES MATCH
CE"A"
tAPS
(2)
CE"B"
tBAC tBDC
2943 drw 15
BUSY"B"
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING(1)
ADDR"A" tAPS ADDR"B"
(2)
ADDRESS "N"
MATCHING ADDRESS "N" tBAA tBDA
2943 drw 16
BUSY"B"
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. If tAPS is not satisfied, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT70V07X25 Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 -- -- -- -- 25 30 0 0 -- -- -- -- 30 35 0 0 -- -- -- -- 40 45 ns ns ns ns
2942 tbl 14
IDT70V07X35 Min. Max.
IDT70V07X55 Min. Max. Unit
Parameter
Min.
Max.
NOTE: 1. "X" in part numbers indicates power rating (S or L).
6.37
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF INTERRUPT TIMING(1)
tWC ADDR"A" tAS
(3)
INTERRUPT SET ADDRESS (2) tWR (4)
CE"A"
R/W"A" tINS (3)
INT"B"
2943 drw 17
tRC ADDR"B" INTERRUPT CLEAR ADDRESS(2) tAS(3)
CE"B"
OE"B"
tINR(3)
INT"B"
2943 drw 18
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. See Interrupt truth table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES TRUTH TABLE III -- INTERRUPT FLAG(1)
W R/WL
L X X X
Left Port
Right Port A14L-A0L 7FFF X X 7FFE
CE CEL
L X X L
OE OEL
X X X L
INT INTL
X X L
(3) (2)
W R/WR
X X L X
CE CER
X L L X
OE OER
X L X X
A14R-A0R X 7FFF 7FFE X
INT INTR
L(2) H(3) X X
Function Set Right INTR Flag Set Left INTL Flag Reset Right INTR Flag Reset Left INTL Flag
2942 tbl 15
H
NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change.
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE IV -- ADDRESS BUSYARBITRATION
Inputs
CEL CE CER CE
Outputs
BUSYL BUSY
A0L-A14L A0R-A14R
NO MATCH MATCH MATCH MATCH
(1)
BUSYR BUSY
(1)
Function Normal Normal Normal Write Inhibit(3)
X H X L
X X H L
H H H (2)
H H H (2)
NOTES: 2943 tbl 16 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
TRUTH TABLE V -- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D7 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D7 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free
2943 tbl 17
Status
NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V07. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
The IDT70V07 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V07 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted.
7FFF location 7FFF. The message (8 bits) at 7FFE or 7FFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFE and 7FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table for the interrupt operation.
BUSY LOGIC INTERRUPTS
If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FFE (HEX), where a write is defined as CE = R/W = VIL per the Truth Table. The left port clears the interrupt through access of address location 7FFE when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an
14
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT 70V07 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS
When expanding an IDT70V07 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the
DECODER
MASTER Dual Port RAM
CE
BUSYR
BUSYL
SLAVE Dual Port RAM
CE
BUSYR
BUSYL
MASTER Dual Port RAM
CE
BUSYR
BUSYL
BUSYL
SLAVE Dual Port RAM
CE
BUSYR BUSYR
2943 drw 19
BUSYL
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V07 RAMs.
same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT70V07 RAM the busy pin is an output if the part is used as a master (M/S pin = H), and the busy pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table where CE and SEM are both high. Systems which can best use the IDT70V07 contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V07's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V07 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called "Token Passing Allocation." In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The
15
SEMAPHORES
The IDT70V07 is an extremely fast Dual-Port 32K x 8
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
left processor can then either repeatedly request that semaphore's status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V07 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 - A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table III). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side's output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles.
L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE
D Q
R PORT SEMAPHORE REQUEST FLIP FLOP
Q D
D0 WRITE
SEMAPHORE READ
SEMAPHORE READ
2943 drw 20
Figure 4. IDT70V07 Semaphore Logic
It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue until a one is written to the same semaphore request latch. Should the other side's semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side's request latch. The second side's flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
USING SEMAPHORES--SOME EXAMPLES
Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V07's Dual-Port RAM. Say the 32K x 8 RAM was to be divided into two 16K
16
6.37
IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 16K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 16K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 16K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 16K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was "off-limits" to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory "WAIT" state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
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IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range
Blank
Commercial (0C to +70C)
PF G J
80-pin TQFP (PN80-1) 68-pin PGA (G68-1) 68-pin PLCC (J68-1)
25 35 55
Speed in nanoseconds
S L 70V07
Standard Power Low Power 256K (32K x 8) 3.3V Dual-Port RAM
2943 drw 21
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